In conventional wafer probe operation, it is desirable to simultaneously test a large portion of the dies fabricated on a wafer. Today's technology attempts to maximize the number of dies on the wafer that can be tested in parallel. Using conventional methods, 16 to 32 dies on the same wafer can be tested in parallel (with each die having about 48-60 test pins). Parallel testing is particularly useful when testing dies that have long test cycles. For example, it is desirable to test a large number of non-volatile memory devices in parallel, because the test cycle for these devices is extremely long due to multiple program and erase operations performed during testing.
Methods for increasing the number of dies tested in parallel need to address the following two issues. The probing device must be able to make contact to all of the circuits being tested in parallel. In addition, the tester must be able to process information received from the signal pins of the probing device.
It would therefore be desirable to have improved methods and structures for testing a large number of dies on a wafer in parallel.